Samsung S3C2500B User Manual page 260

MEMORY CONTROLLER
31 30 29 28 27
DW PMC
[3:0] Chip selection hold time on nOE: TCOH
0000 = 0 cycle
0100 = 4 cycles
1000 = 8 cycles
1100 = 12 cycles
[7:4] Chip selection setup time on nOE: TCOS
0000 = 0 cycle
0100 = 4 cycles
1000 = 8 cycles
1100 = 12 cycles
[11:8] Address setup time: TACS
0000 = 0 cycle
0100 = 4 cycles
1000 = 8 cycles
1100 = 12 cycles
[15:12] Page address access cycle: TPA
0000 = 0 cycle
0100 = 4 cycles
1000 = 8 cycles
1100 = 12 cycles
[20:16] Access cycles(nOE low time): TACC
00000 = reserved
00100 = 4 cycles
01000 = 8 cycles
01100 = 12 cycles
10000 = 16 cycles
10100 = 20 cycles
11000 = 24 cycles
11100 = 28 cycles
[22:21] Reserved
[23] nWBE or nBE/DQM selection: IS
0 = nWBE function 1 = nBE function
NOTE: The nWBE signal is operated at only coriting operation.
The nBE/DQM signal is operated at writing and reading operation.
[27:24] Bank Size: BS
0000 = Disable
0100 = 8M
[29:28] Page mode configuration: PMC
00 = Normal ROM or External I/O
10 = 8 word page
[31:30] Physical memory data bus width: DW
00 = Reserved
5-24
24 23 22 21 20
BS IS TACC
0001 = 1 cycle 0010 = 2 cycles
0101 = 5 cycles 0110 = 6 cycles
1001 = 9 cycles 1010 = 10 cycles
1101 = 13 cycles 1110 = 14 cycles
0001 = 1 cycle 0010 = 2 cycles
0101 = 5 cycles 0110 = 6 cycles
1001 = 9 cycles 1010 = 10 cycles
1101 = 13 cycles 1110 = 14 cycles
0001 = 1 cycle 0010 = 2 cycles
0101 = 5 cycles 0110 = 6 cycles
1001 = 9 cycles 1010 = 10 cycles
1101 = 13 cycles 1110 = 14 cycles
0001 = 1 cycle 0010 = 2 cycles
0101 = 5 cycles 0110 = 6 cycles
1001 = 9 cycles 1010 = 10 cycles
1101 = 13 cycles 1110 = 14 cycles
00001 = reserved 00010 = reserved
00101 = 5 cycles 00110 = 6 cycles
01001 = 9 cycles 01010 = 10 cycles
01101 = 13 cycles 01110 = 14 cycles
10001 = 17 cycles 10010 = 18 cycles
10101 = 21 cycles 10110 = 22 cycles
11001 = 25 cycles 11010 = 26 cycles
11101 = 29 cycles 11110 = 30 cycles
0001 = 1M 0010 = 2M
0101 = 16M 0110-1111 = Reserved
01 = 4 word page
11 = 16 word page
01 = 8-bit 10 = 16-bit
Figure 5-11. Bank n Control (BnCON) Register Configuration
16 15 12 11
TPA TACS
0011 = 3 cycles
0111 = 7 cycles
1011 = 11 cycles
1111 = 15 cycles
0011 = 3 cycles
0111 = 7 cycles
1011 = 11 cycles
1111 = 15 cycles
0011 = 3 cycles
0111 = 7 cycles
1011 = 11 cycles
1111 = 15 cycles
0011 = 3 cycles
0111 = 7 cycles
1011 = 11 cycles
1111 = 15 cycles
00011 = 3 cycles
00111 = 7 cycles
01011 = 11 cycles
01111 = 15 cycles
10011 = 19 cycles
10111 = 23 cycles
11011 = 27 cycles
11111 = 31 cycles
0011 = 4M
11 = 32-bit
8 7 4 3
TCOS TCOH
S3C2500B
0