Table of Contents
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Chapter 4
4.1 Overview .......................................................................................................................................... 4-1
4.2 Features............................................................................................................................................ 4-1
4.3 Address Map..................................................................................................................................... 4-2
4.4 Remap of Memory Space ................................................................................................................. 4-3
4.5 External Address Translation ............................................................................................................ 4-3
4.6 Arbitration Scheme ........................................................................................................................... 4-4
4.6.1 Problem Solvings with Programmable Round-Robin .............................................................. 4-7
4.7 Clock Configuration........................................................................................................................... 4-9
4.8 External Bus Master.......................................................................................................................... 4-14
4.9 System Configuration Special Registers............................................................................................ 4-15
4.9.1 System Configuration Register............................................................................................... 4-16
4.9.2 Product Code and Revision Number Register ........................................................................ 4-18
4.9.3 Clock Control Register ........................................................................................................... 4-19
4.9.4 Peripheral Clock Disable Register.......................................................................................... 4-20
4.9.5 Clock Status Register ............................................................................................................ 4-21
4.9.6 AHB Bus Master Priority Register .......................................................................................... 4-21
4.9.7 Core PLL Control Register ..................................................................................................... 4-22
4.9.8 System Bus PLL Control Register .......................................................................................... 4-23
4.9.9 USB PLL Control Register ..................................................................................................... 4-24
4.9.10 PHY PLL Control Register.................................................................................................... 4-24
Chapter 5
5.1 Overview .......................................................................................................................................... 5-1
5.2 Features............................................................................................................................................ 5-2
5.3 Memory Map..................................................................................................................................... 5-3
5.4 Bus Interface Signals ........................................................................................................................ 5-5
5.5 Endian Modes ................................................................................................................................... 5-7
5.6 Ext I/O Bank Controller ..................................................................................................................... 5-13
5.6.1 Features ................................................................................................................................ 5-13
5.6.2 External Device Connection................................................................................................... 5-14
5.6.3 Ext. I/O Bank Controller Special Register............................................................................... 5-21
5.6.4 Timing Diagram ..................................................................................................................... 5-29
5.7 SDRAM Controller ............................................................................................................................ 5-38
5.7.1 Features ................................................................................................................................ 5-38
5.7.2 SDRAM Size and Configuration ............................................................................................. 5-39
5.7.3 Address Mapping ................................................................................................................... 5-42
5.7.4 SDRAM Commands............................................................................................................... 5-44
5.7.5 External Data Bus Width........................................................................................................ 5-45
5.7.6 Merging Write Buffer ............................................................................................................. 5-45
5.7.7 Self Refresh........................................................................................................................... 5-45
5.7.8 Basic Operation ..................................................................................................................... 5-46
5.7.9 SDRAM Special Registers ..................................................................................................... 5-47
5.7.10 SDRAM Controller Timing.................................................................................................... 5-54
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Table of Contents
(Continued)
S3C2500B RISC MICROCONTROLLER
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