Samsung S3C2500B User Manual page 24

Figure
Number
14-11
14-12
14-13
14-14
14-15
14-16
14-17
14-18
14-19
14-20
14-21
14-22
14-23
14-24
15-1
15-2
15-3
15-4
15-5
15-6
16-1
16-2
16-3
16-4
16-5
17-1
17-2
17-3
17-4
17-5
17-6
17-7
19-1
S3C2500B RISC MICROCONTROLLER
List of Figures
AutoBaud Boundary Regsiter Range ......................................................................14-22
High-Speed UART AutoBaud Boundary Register....................................................14-22
Example of AutoBaud Table Register Setting .........................................................14-23
High-Speed UART AutoBaud Boundary Register....................................................14-23
When Signal is Asserted During Transmit Operation ..............................................14-25
When CTS Signal is Deasserted During Transmit Operation ..................................14-25
Normal Received Rx Data......................................................................................14-26
DCD Lost During Rx Data Receive.........................................................................14-26
Interrupt-Based Serial I/O Transmit and Receive Timing Diagram..........................14-27
DMA-Based Serial I/O Timing Diagram (Tx Only)...................................................14-28
DMA-Based Serial I/O Timing Diagram (Rx Only) ..................................................14-28
Serial I/O Frame Timing Diagram (Normal High-Speed UART) ..............................14-29
Infra-Red Transmit Mode Frame Timing Diagram...................................................14-29
Infra-Red Receive Mode Frame Timing Diagram ...................................................14-30
I/O Port Mode Registers 1/2 ...................................................................................15-4
I/O Function Control Register 1 ..............................................................................15-6
I/O Function Control Register 2 ..............................................................................15-7
I/O Port Control Register for GDMA........................................................................15-8
I/O Port Control Register for External Interrupt .......................................................15-10
I/O Port External Interrupt Clear Register ...............................................................15-11
Internal Interrupt Mode Register .............................................................................16-4
External Interrupt Mode Register ............................................................................16-5
Internal Interrupt Mask Register..............................................................................16-6
External Interrupt Mask Register ............................................................................16-7
Interrupt Priority Register........................................................................................16-8
Timer Output Signal Timing....................................................................................17-2
32-Bit Timer Block Diagram ...................................................................................17-3
Timer Mode Register..............................................................................................17-5
Timer Data Registers..............................................................................................17-6
Timer Counter Registers.........................................................................................17-7
Timer Interrupt Clear Register ................................................................................17-8
Watchdog Timer Register.......................................................................................17-9
272-BGA-2727-AN Package Dimensions................................................................19-2
(Concluded)
Title Page
Number
xxiii