Samsung S3C2500B User Manual page 468

USB CONTROLLER
Bit Number Bit Name
[26] In mode, UNDER
run (IUNDER)
[27] In mode, Fifo
FLUSH (IFFLUSH)
[28] In mode, SenD
STALL (ISDSTALL)
[29] In mode, SenT
STALL (ISTSTALL)
[30] In mode, CLear
data TOGgle
(ICLTOG)
[31] Reserved
10-28
Table 10-18. USBEP1CSR Register Description (Continued)
MCU
R/C
R/W
R/W
R/C
W
USB
S This bit is valid only when endpoint 1 is set to IN
ISO.
The USB sets this bit when in ISO mode, an IN
token is received and the IINRDY bit is not set.
The USB sends a zero length data packet for such
conditions, and the next packet that is loaded into
the FIFO is flushed.
C This bit is valid only when endpoint 1 is set to IN.
The MCU sets this bit if it intends to flush the IN
FIFO. This bit is cleared by the USB when the FIFO
is flushed. The MCU is interrupted when this
happens. If a token is in progress, the USB waits
until the transmission is complete before the FIFO
is flushed. If two packets are loaded into the FIFO,
only the top-most packet (one that was intended to
be sent to the host) is flushed, and the
corresponding IINRDY bit for that packet is cleared.
R This bit is valid only when endpoint 1 is set to IN.
The MCU writes a 1 to this register to issue a
STALL handshake to the USB.
The MCU clears this bit to end the STALL condition.
S This bit is valid only when endpoint 1 is set to IN.
The USB sets this bit when a STALL handshake is
issued to an IN token, due to the MCU setting
SEND STALL bit. When the USB issues a STALL
handshake, IINRDY is cleared.
R/C This bit is valid only when endpoint 1 is set to IN.
When the MCU writes a 1 to this bit, the data toggle
bit is cleared. This is a write-only register.
S3C2500B
Description