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S3C2500B
10.4 USB BLOCK DESCRIPTIONS
10.4.1 USB BLOCK OVERVIEW
USB block is compatible with USB spec 1.1. There're 5 EPs (Endpoint) with EP0 for control transfer. This block
uses two input clocks, 133MHz and 48MHz. 133MHz clock is used to special registers access and USB-to-system
bus interfacing. 48MHz clock is used for SIE. 12MHz clock is generated from 48MHz and used for transmitting
data throughout physical cable. FIQ / IRQ interrupt routine should be used for USB service. Max packet size is
programmable with special registers.
D+(out)
D-(out)
D+(in)
D-(in)
rxd
10.4.2 SIE (SERIAL INTERFACE ENGINE) BLOCK
The SIE is the front-end of this hardware and handles most of the protocol described in chapter 8 of the USB
specification. The SIE typically comprehends signaling up to the transaction level. The functions that it handles
could include:
•
Packet recognition, transaction sequencing
•
SOP, EOP, RESET, RESUME signal detection/generation
•
Clock/Data separation
•
NRZI Data encoding/decoding and bit-stuffing
•
CRC generation and checking (Token and Data)
•
Packet ID (PID) generation and checking/decoding
•
Serial-Parallel/Parallel-Serial Conversion
Endpoint 0 FIFO
8
SIE
SIE
8
I/F
8
Figure 10-4. USB Core Block Diagram
Endpoint 1 FIFO
Endpoint 2 FIFO
Endpoint 3 FIFO
Endpoint 4 FIFO
General Function Interface
Special Registers
USB CONTROLLER
32
MUX
32
APB
I/F
32
10-7
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