Data Buffer Descriptor - Samsung S3C2500B User Manual

HDLC CONTROLLER S3C2500B

8.5.8 DATA BUFFER DESCRIPTOR

Rx BDMA function is enabled by DRxEN bit(HCON[7]). When Rx BDMA is enabled, the BDMA fetches the Rx
Buffer Data pointer and Owner bit of the next word. Then it checks the Ownership of the Buffer Descriptor. If the
Owner bit is '1', then BDMA owns the Buffer Descriptor, and BDMA waits until Rx. frame is received. If the entire
frame is received successfully, the status bits in the receive buffer descriptor are set to indicate the received
frame status. The ownership bit in the buffer descriptor pointer is cleared by the CPU which has the ownership
and an interrupt may now be generated. After stores the states, the BDMA fetches next Buffer Data Pointer and
Owner bit of the next word. If the Owner bit is '0'(when BDMA checks the Owner of the Buffer Descriptor), then it
has two options:
— Skip to the next buffer descriptor when DRxnSTSK/DTxnSTSK bit is '1'(Not Owner Skip)
— Generate an interrupt and halt the DMA operation when DRxSTSK/DTxnSTSK bit is '0'(Not Owner Stop)
You must set HBRXBDMAXCNT/HBTXBDMAXCNT register which shows the maximum buffer descriptor counts.
And if all buffer descirptors are used by the received frames or by the transmitted frames, then first Rx/Tx Buffer
Descritptor is fetched by the BDMA.
As BDMA receives the data, the software sets the maximum frame length register. If the received data is longer
than the value of the maximum frame length register, this frame is ignored and the FLV bit is set. The software
also sets the DMA Rx buffer descriptor pointer to point to a chain of buffer descriptors, all of which have their
ownership bit.
The DMA controller can be started to set the DMA Rx enable bit in the control register. When a frame is
received, it is moved into memory at the address specified by the DMA Rx data buffer pointer. If a frame is
longer than the value of the RxBuf Size register, then the next buffer descriptors are fetched to receive the
frame.
That is, to handle a frame, one or more buffer descriptors could be used. Please note that no configurable offset
or page boundary calculation is required. The received frame is moved to the buffer memory whose address is
pointed to by the buffer data pointer until the end of frame, or until the length exceeds the maximum frame length
configured.If the length exceeds the maximum frame length configured, the frame length violated bit is set.
During transmission, the two-byte frame length at the Tx buffer descriptor is moved to the DMA internal Tx
register. After transmission, the Tx status is saved in the Tx buffer descriptor. After stores the status, the BDMA
controller fetches the next buffer descriptor and the Owner bit and the control bits of the next word.
When the DMA Tx buffer descriptor register points to the first buffer descriptor, the transmitter starts transmitting
the frame data from the buffer memory to Tx FIFO.
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