Samsung S3C2500B User Manual page 344

ETHERNET CONTROLLER
7.4.2.11 MAC Missed Error Count Register
The value in the missed error count register, MISSCNT, indicates the number of frames that were discarded due
to various type of errors. Together with status information on frames transmitted and received, the missed error
count register and the two pause count registers provide the information required for station management.
Reading the missed error counter register clears the register. It is then the responsibility of software to maintain a
global count with more bits of precision.
The counter rolls over from 0x7FFF to 0x8000 and sets the corresponding bit in the MAC control register. It also
generates an interrupt if the corresponding interrupt enable bit is set. If station management software wants more
frequent interrupts, you can set the missed error count register to a value closer to the rollover value of 0x7FFF.
For example, setting a register to 0x7F00 would generate an interrupt when the count value reaches 256
occurrences.
Registers Address
MISSCNTA 0xF00B003C
MISSCNTB 0xF00D003C R(Clr)/W
Bit Number
[15:0] Missed error count
[31:16]
7-34
Table 7-46. MISSCNT Register
R/W
R(Clr)/W
Table 7-47. Missed Error Count Register Description
Bit Name
(MissErrCnt)
Reserved
Description
Missed error count
Missed error count
The number of valid packets rejected by the MAC unit
because of MAC RxFIFO overflows, parity errors, or because
the MRxEn bit was cleared. This count does not include the
number of packets rejected by the CAM.
Not applicable.
Description
S3C2500B
Reset Value
0x00000000
0x00000000