Samsung S3C2500B User Manual page 102

PROGRAMMER' ' S MODEL
2.16.1.2 Register 0: Cache type
This is a read-only register which allows operating systems to establish how to perform operations such as cache
cleaning and lockdown. Future ARM cached processors will contain this register, allowing RTOS vendors to
produce future-proof versions of their operating systems.
The cache type register is accessed by reading CP15 register 0 with the opcode_2 field set to 1. For example:
MRC p15, 0, rd, c0, c0, 1; returns Cache type register
The register contains information about the size and architecture of the caches. The format of the register is
shown in Table 2-7.
Register Bits
31:29 Reserved
28:25 Cache type
24 Harvard/Unified
23:21 Reserved
20:18 DCache size
17:15 DCache associativity
14 DCache base size
13:12 DCache words per line
11:9 Reserved
8:6 ICache size
5:3 ICache Associativity
2 ICache base size
1:0 ICache words per line
2-22
Table 2-7. Cache Type Register Format
Meaning Value
000
0111
1 (defines Harvard cache)
000
011 (defines 4KB)
110 (defines 64 way)
0 (defines 1x base parameters)
01 (defines 4 words per line)
000
011 (defines 4KB)
110 (defines 64 way)
0 (defines 1x base parameters)
01 (defines 4 words per line)
S3C2500B