Samsung S3C2500B User Manual page 256

MEMORY CONTROLLER
Figure 5-9. illustrates a connection between S3C2500B and muxed bus ROM & SRAM.
Figure 5-9. ROM & SRAM with Muxed Address & Data Bus Connection
If the external I/O use nReady signal insteady of nWait, you must select nReady in WAITCON register of
memory controller.
ADDR[23] bit is used the address latch enable(ALE) signal to latch an address for the ROM and SRAM
which have the muxed bus structure.
5-20
S3C2500B
ADDR[23]/ALE
DATA[7:0]
nOE
nRCS
nWBE
nREADY
NOTE
ALE
DATA[7:0]
nOE
nCS
nWBE
nREADY
S3C2500B