Samsung S3C2500B User Manual page 420

IOM2 CONTROLLER S3C2500B
9.3.7.3 Monitor channel collision detection
When more than two devices is attached to IOM2-bus, the S3C2500B resolves the collision by waiting inactive in
the MX/MR bits before sending and a per bit check on the transmitted data.
Monitor channel access priority is determined by the address of the monitor message contained in the first
monitor byte transmitted. Once the transmitter detects inactive and starts to transmit the first byte, a per bit check
is performed on each transmitted monitor bit. If any bit mismatches, the transmitter immediately withdraws from
the monitor channel by setting the all remaining bits to 1, the monitor channel collision detection interrupt is
generated and the transmitter reverts back to waiting for the idle condition.
9.3.7.4 C/I Channel Operation
The C/I0 channel carries the commands and indications between the S3C2500B and layer-1 device to control the
activation/deactivation procedures. C/I0 channel access may be arbitrated via in the TIC bus access protocol.
The CPU have access to C/I0 channel by using two registers, IOM2CITD0(in transmit direction) and
IOM2CIRD0(in receive direction). The data written to IOM2CITD0 is continuously transmitted until new data is to
be sent. The IOM2 receiver generates interrupt whenever the receive data changes and is stable for two frames
(double last look criterion).
The C/I1 channel carries the real time status information between the S3C2500B and IOM2 devices other than
layer-1 device. The C/I1 channel is accessed via IOM2CITD1 and IOM2CIRD1.
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