Samsung S3C2500B User Manual page 342

ETHERNET CONTROLLER
7.4.2.9 MAC Station Management Data Control and Address Register
The MAC controller provides support for reading and writing station management data to the PHY. Setting
options in station management registers does not affect the controller. Some PHYs may not support the option to
suppress preambles after the first operation.
Registers Address
STACONA 0xF00B001C
STACONB 0xF00D001C
Bit Number
[4:0] PHY register address
(MPHYRegAddr)
[9:5] PHY address (MPHYaddr)
[10] Write (MPHYwrite)
[11] Busy bit (MPHYbusy)
[12] Reserved
[15:13] MDC clock rate (MMDCrate)
[31:16] Reserved
7-32
Table 7-42. STACON Register
R/W
R/W
R/W
Table 7-43. STACON Register Description
Bit Name
A 5-bit address, contained in the PHY, of the register to be
read or written.
The 5-bit address of the PHY device to be read or written.
To initiate a write operation, set this bit to '1'. For a read
operation, clear it to '0'.
To start a read or write operation, set this bit to '1'. The MAC
controller clears the Busy bit automatically when the operation
is completed.
Not applicable
Controls the MDC period. The default value is '011'.
MDC period = MMDCrate × 4 + 32
Example) MMDCrate = 011,
Not applicable.
Description
Station management control and address
Station management control and address
MDC period = 44 x (1/system clock)
Description
S3C2500B
Reset Value
0x00006000
0x00006000