Samsung S3C2500B User Manual page 211

S3C2500B
3.39.2.2 ARM Code
signed_divide
ANDS
RSBMI
EORS
;ip bit 31 = sign of result
;ip bit 30 = sign of a2
RSBCS
;Central part is identical code to udiv (without MOV a4, #0 which comes for free as part of signed entry sequence)
MOVS
BEQ
just_l
CMP
MOVLS
BLO
div_l
CMP
ADC
SUBCS
TEQ
MOVNE
BNE
MOV
MOVS
RSBCS
RSBMI
MOV
a4, a1, #&80000000
a1, a1, #0
ip, a4, a2, ASR #32
a2, a2, #0
a3, a1
divide_by_zero
a3, a2, LSR #1
a3, a3, LSL #1
s_loop
a2, a3
a4, a4, a4
a2, a2, a3
a3, a1
a3, a3, LSR #1
s_loop2
a1, a4
ip, ip, ASL #1
a1, a1, #0
a2, a2, #0
pc, lr
; Effectively zero a4 as top bit will be shifted out later
; Justification stage shifts 1 bit at a time
; NB: LSL #1 is always OK if LS succeeds
INSTRUCTION SET
3-99