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SYSTEM CONFIGURATION
S3C2500B
4.8 EXTERNAL BUS MASTER
The S3C2500 allows the external bus master to get the external memory bus and control the external memory
system. When the external bus master asserts XBMREQ to get the external memory bus, the S3C2500 asserts
XMBACK high and drives the state of the external memory bus to high impedance after S3C2500 finishes
current transfer with memory. When the external bus master takes the control of external memory bus, it should
take care of SDRAM refresh operation. S3C2500 can get the control of the memory bus 1 cycle after XBMREQ is
deactivated.
HCLK
PXBMREQ
PXBMACK
Figure 4-6. External Master Request Timing
4-14
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