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INTERRUPT CONTROLLER
31
30
29
28
X X
INTMOD
X
[31:0] Internal interrupt mode bits
NOTE:
16-4
27
26
25
24
23
22
21
X
X
X
X
X
X
X
X
Each of the 32 bits in the interrupt mode enable register, INTMOD,
corresponds to an interrupt source. When the source interrupt mode bit
is set to 1, the interrupt is processed by the ARM940T core in FIQ
(fast interrupt) mode. Otherwise, it is processed in IRQ mode (normal
interrupt). The 32 interrupt sources are mapped as follows:
[31] Watchdog Timer interrupt
(0 = IRQ interrupt mode, 1 = FIQ interrupt mode)
[30] 32-bit Timer 5 interrupt
[29] 32-bit Timer 4 interrupt
[28] 32-bit Timer 3 interrupt
[27] 32-bit Timer 2 interrupt
[26] 32-bit Timer 1 interrupt
[25] 32-bit Timer 0 interrupt
[24] GDMA channel 5 interrupt
[23] GDMA channel 4 interrupt
[22] GDMA channel 3 interrupt
[21] GDMA channel 2 interrupt
[20] GDMA channel 1 interrupt
[19] GDMA channel 0 interrupt
[18] DES interrupt
[17] Ethernet 1 RX interrupt
[16] Ethernet 1 TX interrupt
[15] Ethernet 0 RX interrupt
[14] Ethernet 0 TX interrupt
[13] HDLC 2 RX interrupt
[12] HDLC 2 TX interrupt
[11] HDLC 1 RX interrupt
[10] HDLC 1 TX interrupt
[9] HDLC 0 RX interrupt
[8] HDLC 0 TX interrupt
[7] USB interrupt
[6] CUART RX interrupt
[5] CUART TX interrupt
[4] HUART 1 RX interrupt
[3] HUART 1 TX interrupt
[2] HUART 0 RX interrupt
[1] HUART 0 TX interrupt
[0] IIC interrupt
Figure 16-1. Internal Interrupt Mode Register (INTMOD)
14
13
20
19
18
17
16
15
X
X
X
X
X
X
X
X
12
11
10
9
8
7
6
5
X
X
X
X
X
X
X
X
S3C2500B
4
3
2
1
0
X
X
X
X
X
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