Samsung S3C2500B User Manual page 112

PROGRAMMER' ' S MODEL
2.16.1.10 Register 15: Test/debug register
The DTRRobin and ITRRobin bits set the respective caches into a pseudo round-robin replacement mode.
All defined bits in the control register are set to zero at reset.
2.16.1.11 Reserved Registers
Accessing a reserved register is unpredictable.
2-32
Table 2-22. CP15 Register 15
Register bit
31:4
3
2
1:0
Function
Reserved
ITRRobin
DTRRobin
Reserved
S3C2500B