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USB CONTROLLER
10.5.7 USB ENDPOINT 0 COMMON STATUS REGISTER
This register includes the control bits, status bits, and max packet size value for endpoint 0.
Register
Address
USBEP0CSR
0xF00E0018
Bit Number
Bit Name
[3:0]
MAXP size
value (MAXP)
[6:4]
Reserved
[7]
MAXP size
SETtable
(MAXPSET)
[23:8]
Reserved
[24]
Out packet
ReaDY
(ORDY)
[25]
IN packet
ReaDY
(INRDY )
[26]
SenT STALL
(STSTALL)
10-22
Table 10-15. USBEP0CSR Register
R/W
R/W
USB Endpoint 0 Common Status Register
Table 10-16. USBEP0CSR Register Description
MCU
USB
R/W
R
W
–
R
S
R/S
C
R/C
S
Description
Description
If MAXP[3:0] is 0000, then MAXPsize is 0 byte
If MAXP[3:0] is 0001, then MAXPsize is 8 bytes
If MAXP[3:0] is 0010, then MAXPsize is 16 bytes
If MAXP[3:0] is 0011, then MAXPsize is 24 bytes
If MAXP[3:0] is 0100, then MAXPsize is 32 bytes
If MAXP[3:0] is 0101, then MAXPsize is 40 bytes
If MAXP[3:0] is 0110, then MAXPsize is 48 bytes
If MAXP[3:0] is 0111, then MAXPsize is 56 bytes
If MAXP[3:0] is 1000, then MAXPsize is 64 bytes
0 = USBEP0CSR[3:0] isn't overwritten when MCU
writes a 32bit value to USBEP0CSR register.
1 = USBEP0CSR[3:0] is overwritten.
This is a Read Only bit.
The USB sets this bit once a valid token is written to
the FIFO. An interrupt is generated when the USB sets
this bit. The MCU clears this bit by writing a 1 to the
SVORDY
The MCU sets this bit after writing a packet of data
into endpoint 0 FIFO.
The USB clears this bit once the packet has been
successfully sent to the host.
An interrupt is generated when the USB clears this bit,
so the MCU can load the next packet.
For a zero length data phase, the MCU sets INRDY
and DEND at the same time.
The USB sets this bit if a control transaction is ended
due to a protocol violation. An interrupt is generated
when this bit is set.
S3C2500B
Reset Value
0x00000001
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