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S3C2500B
1.2 FEATURES (Continue)
IOM2 Controller
•
IOM2 terminal mode support
•
Inter-device communication via IC channel
•
TIC bus access control
•
Monitor channel collision control
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Optional signals such as BCL and STRB
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Bus Deactivation/Activation via C/I0
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Bus Reversal
Universal Asynchronous Receiver Transmitter
(UART)
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Programmable baud rates
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32-byte Transmit FIFO and 32-byte Receive
FIFO
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UART source clock selectable (Internal clock :
PCLK2, External clock: EXT_UCLK)
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Auto baud rate detection
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Infra-red (IR) transmit/receive
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Insertion of one or two Stop bits per frame
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Selectable 5-bit, 6-bit, 7-bit, or 8-bit data
transfers
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Parity checking
DES/3DES Accelerator
•
DES or Triple DES mode
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ECB or CBC mode
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Encryption or decryption support
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General DMA support
General DMA Channels
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Six GDMA channels
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Memory to memory data transfer
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Memory to peripheral data transfer (high-speed
UART, DES, and USB controller)
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Support for four external GDMA requests from
GDMA request pins
(xGDMA_Req0 - xGDMA_Req3).
Six Programmable Timers
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Interval or toggle mode operation
Hardware Watchdog Timer
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Useful for periodic reset or interrupts
Programmable Interrupt Controller
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39 programmable interrupt sources
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33 internal sources and 6 external sources
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programmable priority control
Programmable I/O port Controller
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64 programmable I/O ports
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Individually configurable to input, output, or I/O
mode for dedicated signals
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6 external interrupt request
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4 external GDMA request
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4 external GDMA acknowledge
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6 timer outputs
•
14 UART signals
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22 HDLC signals
PRODUCT OVERVIEW
1-3
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