Samsung S3C2500B User Manual page 359

S3C2500B
7.5.4.2 Reporting of Reception Errors
When it detects a start of frame delimiter (SFD), the MAC starts putting data it has received from the MII into the
MRxFIFO. It also checks for internal errors (MRxFIFO overruns) while reception is in progress.
When the reception process is completed, the MAC checks for external errors, such as frame alignment, length,
CRC, and frame too long.
The following is a description of the types of errors that may occur during a receive operation:
Parity error
Frame Alignment Error
CRC Error
Frame too long
MRxFIFO full
MII error
A parity bit protects each byte in the MRxFIFO. If a parity error occurs, it is
reported to the MAC. A detected parity error sets the RxParErr bit in the
BMRXSTAT register.
After receiving a frame, the receiver block checks that the incoming frame
(including CRC) was correctly framed on an 8-bit boundary. If it is not and if the
CRC is invalid, data has been disrupted through the network, and the receive
block reports a frame alignment error. A CRC error is also reported.
After receiving a frame, the receiver block checks the CRC for validity, and
reports a CRC error if it is invalid. The PHY informs the MAC if it detects a
medium error (such as a coding violation) by asserting the input pin RX_ER.
When the MAC sees RX_ER asserted, it sets CRCErr bit of the BMRXSTAT
register.
The receiver block checks the length of the incoming frame at the end of
reception (including CRC, but excluding preamble and SFD). If the length is
longer than the maximum frame size of 1518 bytes, the receiver block reports
receiving a 'long frame' , unless long frame mode is enabled. The receiver can
detect network-related errors such as CRC, frame alignment, and length errors.
It can also detect these types of errors in the following combinations:
— CRC errors only
— Frame alignment and CRC errors only
— Length and CRC errors only
— Frame alignment, length, and CRC errors
During the reception, the incoming data are put into the MRxFIFO temporarily
before they are transferred to the system memory. If the MRxFIFO is filled up
because of excessive system latency or for other reasons, the receiver block
sets the overrun bit in the BMRXSTAT register.
The PHY informs the MAC if it detects a medium error (such as a coding
violation) by asserting the input pin Rx_er. When the MAC sees Rx_er asserted,
it sets CRCErr bit of the receive status register.
ETHERNET CONTROLLER
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