High-Speed Uart Operation; Fifo Operation; Hardware Flow Control - Samsung S3C2500B User Manual

SERIAL I/O (HIGH-SPEED UART) S3C2500B

14.4 HIGH-SPEED UART OPERATION

Data Transmit Operation Flow:
If there is no data at Tx Buffer FIFO of High-Speed UART (in case of FIFO, if data in the Tx FIFO are empty as
same amount of trigger level), High-Speed UART generates interrupt or GDMA request signal. It depends on
High-Speed UART mode. CPU(or software) or GDMA controller will read data from memory where High-Speed
UART transmit data are stored, and send them to Tx Buffer/FIFO. Transfer unit is byte. When data come from
High-Speed UART Rx pin, data are stored to Rx Buffer/FIFO, via shift register. If valid Rx data are received,
High-Speed UART generates interrupt or GDMA request signal. (Similar to Tx Block, in case of FIFO, it is same
as Tx block. Data should be stored as the same level of trigger level.) If there is an error on Rx data, High-Speed
UART does not generate GDMA request signal but generates interrupt even in case of GDMA mode.
(Although High-Speed UART is FIFO mode, if error data shift to FIFO top, then High-Speed UART generates
interrupt.) Transfer unit is byte, same as at Tx block.

14.4.1 FIFO OPERATION

Tx FIFO Operation:
If there is no valid data on trigger level of TX FIFO, High-Speed UART generates interrupt (INT_TXD) or sends a
request signal to GDMA. During this operation trigger level should be 30/32 (empty depth/FIFO depth), 24/32,
16/32 or 8/32. CPU or GDMA fills data into TX FIFO by byte.
Rx FIFO Operation:
If received data are filled up to RX FIFO trigger level, High-Speed UART generate interrupt (INT_RXD) or send
request signal to GDMA. The size of transferred data is 1 byte. If RX data contains error in case of GDMA mode
operation, High-Speed UART generates interrupt instead of sending request signal to GDMA. Then CPU
executes interrupt service routine for error data. So GDMA transmits (error free) valid data only from received
data.

14.4.2 HARDWARE FLOW CONTROL

Hardware Flow Control for Transmit Operation:
When CTS signal is asserted during Transmit operation -
High-Speed UART transmits TX DATA to TX line normally.
When CTS signal is deasserted during Transmit operation -
If CTS signal is deasserted when High-Speed UART transmits TX DATA to TX line, High-Speed UART stops data
transmission immediately. In this case, transmitting TX data will be lost.
Hardware Flow Control for Receive Operation:
In the hardware flow control, during High-Speed UART receive data from Rx pin, DCD level have to be low. If
DCD level goes high, received data will be pull up by High-Speed UART Rx block from that time.
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