Samsung S3C2500B User Manual page 247

S3C2500B
Table 5-11 and 5-12.
Using little-endian and half-word access, Program/Data path between register and external memory.
WA=Address whose LSB is 0, 4, 8, C, EA=External Address
HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E
BA=Address whose LSB is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
X=Don't care.
Table 5-11. External 16-bit Datawidth Store Operation with Little-Endian
Transfer Width
Bit Num.
CPU Register Data
CPU Address
Bit Num.
CPU Data Bus
External Address (ADDR)
Bit Num.
External Data
Timing Sequence
Table 5-12. External 16-bit Datawidth Load Operation with Little-Endian
Transfer Width
Bit Num.
CPU Register Data
CPU Address
Bit Num.
CPU Data Bus
External Address (ADDR)
Bit Num.
External Data
Timing Sequence
STORE (CPU Reg → → External Memory)
32-bit
31 0
abcd
WA
31 0
abcd
EA+1 EA
15 0 15 0
ab cd
1st 2nd
LOAD (CPU Reg ← ← External Memory)
32-bit
31 0
abcd
WA
31 0 31 0
abxx abcd
EA + 1 EA
15 0 15 0
ab cd
1st 2nd
16-bit
31 0 31 0
xxab xxxb
HA BA
31 0 31 0
abab bbbb
EA
15 0 15 0
ab xb
16-bit
31 0 31 0
xxab xxxb
HA BA
31 0 31 0
abab bbbb
EA
15 0
ab
MEMORY CONTROLLER
8-bit
31 0
xxxa
BA+1
31 0
aaaa
EA
15 0
ax
8-bit
31 0
xxxa
BA+1
31 0
aaaa
EA
15 0
ab
5-11