Samsung S3C2500B User Manual page 421

S3C2500B
9.3.7.5 TIC Bus Access
The TIC bus capability enables more than one device to access IOM2 bus. The arbitration mechanism is
implemented in the last byte of channel2 of IOM2 interface. This allows external communication controllers (up to
7) to access the C/I0 and D Channel in the channel0 of IOM2 interface. The TIC bus access is enabled by setting
the TICEN to "1".
An access request to the TIC bus may either be generated by the software (CPU access to the C/I channel) or by
the HDLC controller (transmission of HDLC frame in the D channel).
A software access request to the bus is activated by setting the BREQ bit to "1".
In the case of an access request, the IOM2 controller checks the BAC (bit 5 of DU last byte of channel2) for the
status "bus free" (BAC = 1). If the bus is free, the IOM2 controller starts to transmit its own TIC bus address
programmed in the IOM2TBA register. When the IOM2 controller transmits the TIC bus address TAD on DU, it
compares the bit with the value on DU. If any bit mismatches, that is, a sent bit set to "1" is read back as "0", the
IOM2 controller withdraws immediately from the TIC bus. If more than one device attempt to access the bus
simultaneously, the one with the lowest address values wins. If all the TIC bus address bits match, the TIC bus is
immediately occupied by the IOM2 controller by setting the BAC to "0" in the subsequent frame until the access
request is withdrawn. Figure 9-4 shows the channel2 of IOM2 interface.
When the TIC bus is occupied by one device, the bus is identified to other devices as occupied via the BAC ("0").
After a successful bus access, the IOM2 controller is automatically set into a lower priority class, that is, a new
bus access cannot be performed until the status "bus free" is indicated in two consecutive frames.
If none of the devices connected to the IOM interface request access to the D and C/I channels, the TIC bus
address 7 will be present. The device with this address will therefore have access, by default, to the D and C/I
channels.
BAC
Figure 9-4. Structure of Last Byte of Channel 2 on DU
TAD
TIC Bus Address
Bus Access
0 = Occupied
1 = Accessible
IOM2 CONTROLLER
9-7