Samsung S3C2500B User Manual page 288

MEMORY CONTROLLER
5.7.9.3 Refresh Timer Register
The Refresh timer register is 32-bit read/write (some bits are read only) register. This register sets the SDRAM
refresh cycle. The refresh timer register is programmed with the number of system bus clock that should be
counted between SDRAM refresh cycles.
Registers Address
REFREG 0xF0020008
REFREG Bit
REFCYC [15:0]
[31:16]
For refresh period of 15.6us in 16, 64 and 128Mbit, and a system bus clock frequency of 133MHz:
-6
15.6 x 10 x 133 x 10
For refresh period of 7.8us in 256Mbit, and a system bus clock frequency of 133MHz:
-6
7.8 x 10 x 133 x 10
The refresh timer is set to 32 on reset. To ensure a refresh interval of less than 15.6us in 16, 64 and 128Mbit
after reset, The minimum frequency of system bus clock allowed is:
-6
32 / (15.6 x 10 )= 2.1MHz
The refresh timer is set to 32 on reset. To ensure a refresh interval of less than 7.8us in 256Mbit after reset, The
minimum frequency of system bus clock allowed is:
-6
32 / (7.8 x 10 )= 4.2MHz
The refresh register should be written to as early as possible in the system start-up procedure, especially when
clock frequency is very low.
31
[15:0] SDRAM refresh cycle
[31:16] Reserved
5-52
Table 5-27. SDRAM Refresh Timer Register
R/W
R/W Refresh timer register
SDRAM refresh cycle
Reserved
6
= 2075
6
= 1037
RESERVED
Figure 5-25. SDRAM Refresh Timer Register
Description
Description
16 15
R/W Default value
R/W
REFCYC
S3C2500B
Reset value
0x00000020
0x00000020
0