About The Arm940T Programmer's Model - Samsung S3C2500B User Manual

S3C2500B

2.15 ABOUT THE ARM940T PROGRAMMER'S MODEL

The ARM940T cached processor macrocell includes the ARM9TDMI microprocessor core, instruction and data
caches, a write-buffer, and a protection unit for defining the attributes of regions of memory.
The ARM940T incorporates two coprocessors:
•
CP14 which allows software access to the debug communications channel
•
CP15 which allows configuration of the caches, protection unit, and other system options such as big or little
endian operation.
The ARM940T also features an external coprocessor interface which allows the attachment of a closely coupled
coprocessor on the same chip, for example, a floating point unit.
The programmer's model of the ARM940T consists of the programmer's model of the ARM9TDMI with the
following additions and modifications:
•
Memory accesses for instruction fetches and data loads and stores may be cached or buffered. Cache and
write buffer configuration and operation is described in detail in following chapters.
•
The registers defined in CP14 are accessible with MCR and MRC instructions. These are described in Debug
communications channel on page 8-46.
•
The registers defined in CP15 are accessible with MCR and MRC instructions. These are described in
ARM940T CP15 registers on page 2-5.
•
Registers and operations provided by any coprocessors attached to the external coprocessor interface will be
accessible with appropriate coprocessor instructions.
The ARM9TDMI processor core implements ARM Architecture v4T, and so executes the ARM 32-bit instruction
set and the compressed Thumb 16-bit instruction set. The programmer's model is fully described in the ARM
Architecture Reference Manual.
The ARM v4T architecture specifies a small number of implementation options. The options selected in the
ARM9TDMI implementation are listed in Table 2-4. For comparison, the options selected for the ARM9TDMI
implementation are also shown.
Processor Core
ARM7TDMI
ARM9TDMI
The ARM9TDMI is code-compatible with the ARM7TDMI, with two exceptions:
•
The ARM9TDMI implements the base restored data abort model, which significantly simplifies the software
data abort handler.
•
The ARM9TDMI fully implements the instruction set extension spaces added to the ARM (32-bit) instruction
set in architecture v4 and v4T.
These differences are explained in more detail below.
Table 2-4. ARM9TDMI Implementation Option
ARM Data Abort Mode
Architecture
v4T Base updatd
v4T Base restored
PROGRAMMER' ' S MODEL
Value Stored by Direct
STR, STRT, STM of PC
Address of Inst + 12
Address of Inst + 12
2-19