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S3C2500B
HDLC CONTROLLER
8.5 HDLC OPERATIONAL DESCRIPTION
The following sections describe the operation of the HDLC module.
8.5.1 HDLC INITIALIZATION
A power-on or reset operation initializes the HDLC module and forces it into the reset state. After a reset, the
CPU must write a minimum set of registers, as well as any options set, based on the features and operating
modes required.
First, the configuration of the serial port and the clock mode must be defined. These settings include the
following:
— Data format select
— BRG clock select
— DPLL clock select
— Transmit clock select
— Receive clock select
— BRG/DPLL enable to use internal clock
You must also set the clock for various components before each component is enabled. Additional registers may
also have to be programmed, depending on the features you select. All settings for the HDLC mode register,
HMODE, and the HDLC control register, HCON, must be programmed before the HDLC is enabled.
To enable the HDLC module, you must write a '1' to the receiver enable bit and/or the transmitter enable bit.
During normal operation, you can disable the receiver or the transmitter by writing a '0' to the RxEN or TxEN bit,
respectively. You can disable the receiver and HRXFIFO or the transmitter and HTxFIFO by writing a '1' to the
RxRS or TxRS bit, respectively.
8-11
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