Table of Contents
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8.1 Overview .......................................................................................................................................... 8-1
8.2 Features............................................................................................................................................ 8-2
8.3 Function Descriptions........................................................................................................................ 8-3
8.3.1 HDLC Frame Format ............................................................................................................. 8-4
8.4 Protocol Features.............................................................................................................................. 8-6
8.4.1 Invalid Frame ........................................................................................................................ 8-6
8.4.2 Zero Insertion and Zero Deletion............................................................................................ 8-6
8.4.3 Abort...................................................................................................................................... 8-6
8.4.4 Idle and Time Fill ................................................................................................................... 8-6
8.4.5 FIFO Structure....................................................................................................................... 8-7
8.4.6 Two-Channel DMA Engine..................................................................................................... 8-7
8.4.7 Baud Rate Generator............................................................................................................. 8-7
8.4.8 Digital Phase-Locked Loop (DPLL) ........................................................................................ 8-9
8.4.9 Clock Usage Method.............................................................................................................. 8-9
8.5 HDLC Operational Description .......................................................................................................... 8-11
8.5.1 HDLC Initialization ................................................................................................................. 8-11
8.5.2 HDLC Data Encoding/Decoding ............................................................................................. 8-12
8.5.3 HDLC Data Setup and Hold Timing with Clock....................................................................... 8-13
8.5.4 HDLC Transmitter Operation ................................................................................................. 8-14
8.5.5 HDLC Receiver Operation ..................................................................................................... 8-16
8.5.6 Hardware Flow Control .......................................................................................................... 8-17
8.5.7 Memory Data Structure.......................................................................................................... 8-19
8.5.8 Data Buffer Descriptor ........................................................................................................... 8-20
8.6 Buffer Descriptor............................................................................................................................... 8-21
8.6.1 Transmit Buffer Descriptor ..................................................................................................... 8-21
8.6.2 Receive Buffer Descriptor...................................................................................................... 8-22
8.7 HDLC Special Registers.................................................................................................................... 8-24
8.7.1 HDLC Global Mode Register.................................................................................................. 8-27
8.7.2 HDLC Control Register .......................................................................................................... 8-30
8.7.3 HDLC Status Register ........................................................................................................... 8-36
8.7.4 Summary............................................................................................................................... 8-36
8.7.5 HDLC Interrupt Enable Register............................................................................................. 8-42
8.7.6 HDLC Tx Fifo......................................................................................................................... 8-44
8.7.7 HDLC Rx Fifo ........................................................................................................................ 8-45
8.7.8 HDLC Brg Time Constant Registers....................................................................................... 8-46
8.7.9 HDLC Preamble Constant Register........................................................................................ 8-47
8.7.10 HDLC Station Address Registers and Hmask Register ......................................................... 8-48
8.7.11 Dma Tx Buffer Descriptor Pointer Register .......................................................................... 8-49
8.7.12 Dma Rx Buffer Descriptor Pointer Register .......................................................................... 8-50
8.7.13 Maximum Frame Length Register ........................................................................................ 8-50
8.7.14 Receive Buffer Size Register ............................................................................................... 8-51
8.7.15 Synchronization Register ..................................................................................................... 8-51
8.7.16 Transparent Control Register ............................................................................................... 8-52
8.7.17 Tx Buffer Descriptor Count Register..................................................................................... 8-53
8.7.18 Rx Buffer Descriptor Count Register .................................................................................... 8-53
8.7.19 Tx Buffer Descriptor Maximum Count Register .................................................................... 8-54
8.7.20 Rx Buffer Descriptor Maximum Count Register.................................................................... 8-54
x x
Table of Contents
(Continued)
S3C2500B RISC MICROCONTROLLER
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