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S3C2500B
7.3.6 FLOW CONTROL BLOCK
Flow control is done using the MAC control frame. The receiver sends control frames to the transmitter and the
transmitter pauses its operation during the time interval specified in the control frames. The flow control block
provides the following functions:
•
Recognition of MAC control frames received by the receiver block
•
Transmission of MAC control frames, even if transmitter is paused
•
Timers and counters for pause operation
• •
Command and status register (CSR) interface
• •
Options for passing MAC control frames through to software drivers
For details, refer to the full-duplex pause operation section in this chapter.
7.3.7 BUFFERED DMA (BDMA) OVERVIEW
The BDMA engine controls the data feeding and reception between the MAC and the system bus (AMBA) using
two buffers, BDMA TxBUFF (BTxBUFF) and BDMA RxBUFF (BRxBUFF). The BTxBUFF and BRxBUFF hold
data and status information for frames being transmitted and received, respectively. Each buffer is controlled by
the block, which consists of a bus arbiter, a control and status block, buffer descriptors.
7.3.7.1 Bus Arbiter
The bus arbiter decides which of the BDMA buffer controllers, transmit (Tx) or receive (Rx), has the highest
priority for accessing the system bus. The prioritization is dynamic. The BDMA arbiter outputs a bus request
signal (nREQ) to the AMBA when Rx Buffer (BRxBUFF) contains 4-words data, or EOF (End of Frame) was
saved to the buffer, or Tx Buffer (BTxBUFF) contains 4-word free space.
After it receives a bus acknowledgement signal (nACK) from the AMBA, the BDMA bus arbiter determines the
correct bus access priority.
ETHERNET CONTROLLER
7-7
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