Samsung S3C2500B User Manual page 284

MEMORY CONTROLLER
Reg0 Bit
XW [0]
AP [1]
CL [3:2]
D1[1:0] [5:4]
D0[1:0] [7:6]
RP [9:8]
RCD [11:10]
RC [15:12]
RAS [19:16]
[31:20]
NOTES
1. Software should not write to configuration register when the SDRAM engine is busy. The SDRAM engine status
bit, BUSY in command register, can be used to check if the control engine is idle.
2. We recommend that the auto pre-charge should be disabled by asserting "1" on the AP of Reg0 when the page hit ratio
is more than 50%.
5-48
Table 5-25. SDRAM Configuration Register (Continue)
External data bus Width
0 = external bus width is 32-bit.
1 = external bus width is 16-bit.
Auto Pre-charge control for SDRAM accesses
0 = Auto pre-charge
1 = No auto pre-charge
CAS Latency
00 = Reserved
10 = CL: 2 cycles
SDRAM device Density of bank 1
00 = 16M-bit SDRAM memory devices.
01 = 64M-bit SDRAM memory devices.
10 = 128M-bit SDRAM memory devices.
11 = 256M-bit SDRAM memory devices.
SDRAM device Density of bank 0
00 = 16M-bit SDRAM memory devices.
01 = 64M-bit SDRAM memory devices.
10 = 128M-bit SDRAM memory devices.
11 = 256M-bit SDRAM memory devices.
Row Pre-charge time
00 = RP: 1 cycle
10 = RP: 3 cycles
RAS to CAS delay
00 = RCD: 1 cycle
10 = RCD: 3 cycles
Row Cycle
0000 = RC: 1 cycles
...
1110 = RC: 15 cycles
Row Active time
0000 = RAS: 1 cycles
...
1110 = RAS: 15 cycles
Reserved
Description
01 = CL: 1 cycle
11 = CL: 3 cycles
01 = RP: 2 cycles
11 = RP: 4 cycles
01 = RCD: 2 cycles
11 = RCD: 4 cycles
0001 = RC: 2 cycles
1111 = RC: 16 cycles
0001 = RAS: 2 cycles
1111 = RAS: 16 cycles
S3C2500B
R/W Default
value
R/W 0
R/W 0
R/W 11
R/W 00
R/W 00
R/W 11
R/W 11
R/W 1001
R/W 1001
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