Samsung S3C2500B User Manual page 455

S3C2500B
Bit Number Bit Name
[0] EP0Interrupt
(EP0I)
[4:1] EP1Interrupt -
EP4Interrupt
(EP1I - EP4I)
[7:5] Reserved
[8] SUSpend
Interrupt (SUSI)
[9] RESume
Interrupt (RESI)
[10] ReSeT Interrupt
(RSTI)
[11] DISConnect
Interrupt (DISCI)
[31:12] Reserved
Table 10-7. USBINTR Register Description
MCU USB
R/C S
R/C S
R/C S
R/C S
R/C S
R/W C
Description
This bit corresponds to endpoint 0 interrupt.
The USB sets this bit under the following conditions:
1. ORDY bit is set.
2. INRDY bit is cleared.
3. STSTALL bit is set.
4. SETEND bit is set.
5. DEND bit is cleared (Indicates End of control
transfer)
For Bulk Endpoints:
The USB sets this bit under the following conditions:
1. IINRDY bit is cleared.
2. FIFO is flushed.
3. OSTSTALL/ ISTSTALL is set.
For ISO Endpoints:
The USB sets this bit under the following conditions:
1. IUNDER bit is set.
2. IINRDY bit is cleared.
3. FIFO is flushed.
4. OSTSTALL/ ISTSTALL is set.
NOTE: conditions 1 and 2 are mutually exclusive
The USB sets this bit when it receives suspend
signaling. This bit is set whenever there is no activity
for 3ms on the bus. Thus, if the MCU does not stop
the clock after the first suspend interrupt, it will be
continue to be interrupted every 3ms as long as there
is no activity on the USB bus.
By default this interrupt is disabled.
The USB sets this bit, when it receive resume
signaling, while in suspend mode.
If the resume is due to a USB reset, then the MCU is
first interrupted with a Resume Interrupt. Once the
clocks resume and the SE0 condition persists for 3ms,
USB RESET interrupt will be asserted.
The USB sets this bit, when it receives reset signaling.
The USB sets this bit, when it finishes disconnect
operation.
USB CONTROLLER
10-15