Samsung S3C2500B User Manual page 50

PRODUCT OVERVIEW
Group Pin Name
Memory nEWAIT
Interface
(80)
nRCS[7:0]
B0SIZE[1:0]
nOE
nWBE[3:0]/
nBE[3:0]/
DQM[3:0]
1-16
Table 1-1. S3C2500B Signal Descriptions (Continue)
Pin Type Pad Type
1 I
8 O
2 I
1 O
4 O
phicu Not External wait signal.
This signal is activated when an external I/O
device or ROM/SRAM/Flash banks need more
access cycles than those defined in the
corresponding control register.
phot20 Not ROM/SRAM/Flash/ External I/O Chip
select. The S3C2500B supports upt to 8 banks
of ROM/SRAM/Flash/ External I/O. By
controlling the nRCS signals, you can map
CPU address into the physical memory banks.
phic Bank 0 Data Bus Access Size.
Bank0 is used for the boot program. You use
these pins to set the size of the bank 0 data
bus as follows: "01" = Byte, "10" = Half word,
"11" = Word, and "00" = reserved.
phot20 Not output enable.
Whenever a memory read access occurs, the
nOE output controls the output enable port of
the specific memory device.
phot20 Not write byte enable or DQM for SDRAM
Whenever a memory write access occurs, the
nWBE output controls the write enable port of
the specific memory device. DQM is data
input/output mask signal for SDRAM.
S3C2500B
Description