Hdlc Global Mode Register - Samsung S3C2500B User Manual

S3C2500B

8.7.1 HDLC GLOBAL MODE REGISTER

Registers
HMODEA
0×F0100000
HMODEB
0×F0110000
HMODEC 0×F0120000
Bit Bit Name
Number
[0] Multi-Frame in HTxFIFO
in DMA operation (MFF)
[1] Reserved
[2] Rx clock inversion
(RXCINV)
[3] Tx clock inversion
(TXCINV)
[4] Rx Little-Endian mode
(RxLittle)
[5] Tx Little-Endian mode
(TxLittle)
[6] Rx Transparent mode
(RxTRANS)
[7] Tx Transparent mode
(TxTRANS)
[10:8] Tx preamble length
(TxPL)
[11] Reserved
Table 8-7. HMODEA, HMODEB, and HMODEC Register
Address R/W
R/W
R/W
R/W
Table 8-8. HMODE Register Description
If this bit is set, more than one frame can be loaded into HTxFIFO. In this
case, the frame size may be less than the FIFO size.
Not applicable.
If this bit set to '0', the receive clock samples the data at the rising edge.
If this bit set to '1', the receive clock samples the data at the falling edge.
If this bit set to '0', the transmit clock shifts the data at the falling edge.
If this bit set to '1', the transmit clock shifts the data at the rising edge.
This bit determines whether the data is in Little- or Big-endian format.
HRXFIFO is in Little-endian. If this bit is set to '0', then the data on the
system bus should be in Big-endian. Therefore the bytes will be swapped
in Big-endian.
This bit determines whether Tx data is in Little or Big endian (TxLittle)
format. HTxFIFO is in Little-endian. If this bit is set to '1', the data on the
system bus is Little endian. If this bit is set to '0', the data on the system
bus is in Big-endian. (that is, the data bytes are swapped to be Little
endian format.) It is used only by the Transmitter Interrupt Mode, not by
the Transmitter DMA Mode. (see 8-14)
If this bit set to one, HDLC Rx operates transparent mode. Otherwise,
operates HDLC mode
If this bit set to one, HDLC Rx operates transparent mode. Otherwise,
operates HDLC mode
These bits determine the length of preamble to be sent before the
opening flag when the TxPRMB bit is set in the control register.
000 1byte, 001 2bytes, ..., and 111 8bytes will be sent.
Not applicable
Description
HDLC Mode register
HDLC Mode register
HDLC Mode register
Description
HDLC CONTROLLER
Reset Value
0×00000000
0×00000000
0×00000000
8-27