Samsung S3C2500B User Manual page 318

ETHERNET CONTROLLER
7.3.7.2 Control and Status
This block controls the read/write operations of the bus master across the AMBA. The control logic supports the
following operations:
— Fixed 4-word burst size control between Tx and Rx.
— Transmit threshold control (based on 1/8 of transmit buffer size) to match transmission latency to system bus
latency.
— Little-Endian byte swapping, to support the data transfer of Little-Endian memory usage for frame data.
— Big-Endian byte swapping, to support the data transfer of Big-Endian memory usage for frame data.
When memory operate on Big-Endian format and byte unit access, Ethernet transmit(receive) reliable data
by setting BDMATX(RX)CON.7 to '1' .
— A transmit/receive alignment widget to circumvent word alignment restrictions.
The beginning of a frame should be placed on word boundary. Misalignment of the BDMA transfer would
complicate the design of the DMA and degrade the performance. To avoid this, you can use an alignment widget
between the BDMA Buffer (word) and the MAC FIFO (byte) by controlling the widget field in Tx buffer descriptor.
The widget discards the first 'n' bytes (up to three), where 'n' is the value read from the Tx buffer descriptor that
configures the alignment widget.
In the receiver, the BDMA bus arbiter inserts a programmable number of bytes (up to three) into the received
data stream while the preamble is being received. This adds some padding to the beginning of the frame. This
padding can then be used to solve the alignment problem without having to use a copy of the buffer. Because
the data is inserted prior to the concatenation of bytes into words, it does not misalign the subsequent DMA
transfer. The number of the alignment bytes is read from the BDMARXCON.5-4 (BRxWA).
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S3C2500B