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S3C2500B
2
6.4 I
C CONCEPTS
6.4.1 BASIC OPERATION
2
The I
C has two wires, a serial data line (SDL) and a serial clock line (SCL), to carry information between the ICs
connected to the bus. Each IC is recognized by a unique address and can operate as either a transmitter or
receiver, depending on the function of the specific ICs.
2
The I
C is a multi-master bus. This means that more than ICs which are capable of controlling the bus can be
connected to it. Data transfers proceed as follows:
Case 1: A master IC wants to send data to another IC (slave):
1. Master addresses slave
2. Master sends data to the slave (master is transmitter, slave is receiver)
3. Master terminates the data transfer
SDA by
Transmitter
SDA by
Receiver
SCL from
Master
S
Start
Condition
Case 2: A master IC wants to receive information from another IC (slave):
1. Master addresses slave
2. Master receives data from the slave (master is receiver, slave is transmitter)
3. Master terminates the data transfer
Acknowledge
from receiver
MSB
8
1
2
R/W
Address
Figure 6-2. Master Transmitter and Slave Receiver
MSB
9
1
2
ACK
Data
2
I
C CONTROLLER
Acknowledge
from receiver
8
9
ACK
P
Stop
Condition
6-3
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