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MEMORY CONTROLLER

5.2 FEATURES

The following is a list of the Memory Controller's features:
10 banks (8 banks for ROM / SRAM / Flash Memory / External I/O interface, 2 banks for SDRAM interface )
16M-byte maximum address range per bank (24 bit external address pins)
32 bit internal and external data bus
Various timing control options
By generating an external bus request, an external device can access the S3C2500B's external memory
interface pins. In addition, the S3C2500B can access slow external devices by using a WAIT signal. The
WAIT signal, which is generated by the external device, extends the duration of the CPU's memory
access cycle beyond its programmable value.
5-2
NOTE
S3C2500B

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