Samsung S3C2500B User Manual page 354

ETHERNET CONTROLLER
7.5.1.4.2 BDMA/MAC Interface Operation for Reception
The BDI receive operation is a simple FIFO mechanism. The BDMA engine stores received data to MRxFIFO,
and the BDMA RxBUFF controller empties it when the BDMA RxBUFF has enough space left.
Note that the two time domains intersect at the FIFO controller. The writing and reading of data is asynchronous
and on different clocks. Reading is driven by system clock, which is asynchronous to RX_CLK. Writing is driven
by either a 25MHz or a 2.5MHz RX_CLK.
After a reset, the MRxFIFO is empty. To enable the reception, the system must set the receive enable bit in the
MACRXCON register. If the BDMA engine cannot transfer the received data to the BRxBUFF and memory due
to the disabled BDMA or the inaccessibility on the system bus, the MAC RxFIFO may overflow.
7-44
Carrier sense== on
yes
Carrier sense = ON,
after detection SFD,
store byte-stream in in FIFO
Recognize
address?
Move the byte stream in
the FIFO to the receive
buffer memory
Frame too short ?
Frame too long?
Valid FCS ?
Interrput CPU for
handing the frame
Check ethertype or length field
Disassemble frame
Signal to upper layer
Figure 7-11. CSMA/CD Receive Operation
no
Discard the frame
report error status
MAC drive software
(software jobs for typical LAN cards)
S3C2500B