Gdma Control Registers - Samsung S3C2500B User Manual

S3C2500B

12.3.2 GDMA CONTROL REGISTERS

Registers Address
DCON0 0xF0050000
DCON1 0xF0050020
DCON2 0xF0050040
DCON3 0xF0050060
DCON4 0xF0050080
DCON5 0xF00500A0
Bit Number
[0] Run enable/disable
[3:1] GDMA mode selection
Single/Block mode
[4]
Four-data burst mode
[5]
Table 12-3. DCON0/1/2/3/4/5 Registers
R/W
R/W GDMA channel 0 control register
R/W GDMA channel 1 control register
R/W GDMA channel 2 control register
R/W GDMA channel 3 control register
R/W GDMA channel 4 control register
R/W GDMA channel 5 control register
Table 12-4. GDMA Control Register Description
Bit Name
Setting this bit to "1", starts a GDMA operation. To stop GDMA, you
must clear this bit to "0". You can use the DRER (GDMA run enable
register) to manipulate this bit. By using the DRER, other GDMA
control register values are not affected.
6 GDMA modes can initiate a GDMA operation: 1) software mode
(memory-to-memory or memory to/from USB, "000"), 2) an
external GDMA request mode (xGDMA_Req, "001"), 3) HUART TX
mode (HUART from memory, "010"), 4) HUART RX mode (HUART
to memory, "011"), 5) DES IN mode (DES from memory, "100"), 6)
DES OUT mode (DES to memory, "101").
This bit determines the number of external GDMA requests
(xGDMA_Req 0-3) that are required for a GDMA operation. In
Single mode, when [4] = "0", the S3C2500B requires an external
GDMA request for every GDMA operation. In Block mode, when [4]
= "1", the S3C2500B requires only one external GDMA request
during the entire GDMA operation. An entire GDMA operation is
defined as the operation of GDMA until the counter value is zero.
The block mode can be used only when GDMA mode is external
GDMA request mode.
If this bit is set to "1", GDMA operates under four-data burst mode.
Four consecutive source addresses are read and then are written to
the consecutive destination addresses. If four-data burst mode is set
to "1", "Transfer Count Register (DTCR)" should be set carefully
because the four-data burst mode is executed during decreasing of
the transfer count. But the misalign of "Transfer Counter Register
(DTCR)" can be supported. The four-data burst mode can be used
only when GDMA mode is software, external GDMA request, or
DES mode. You can use four-data burst mode together with block
mode of the external GDMA requests.
Description
Description
GDMA CONTROLLER
Reset Value
0×00000000
0×00000000
0x00000000
0x00000000
0x00000000
0x00000000
12-9