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SERIAL I/O (HIGH-SPEED UART)
31
14-12
21
20 19
18 17 16
T
T
T
F
F
H
F
E
E
U
M
L
T
[0] Receive Data Valid (RDV)
0 = No valid data (Receive FIFO-top or HURXBUF)
1 = Valid data present (Receive FIFO-top or HURXBUF)
[1] Break Signal Deteced (BKD)
0 = No Break Signal (Receive FIFO-top or HURXBUF)
1 = Break received
[2] Frame Error (FER)
0 = No Frame Error (Receive FIFO-top or HURXBUF)
1 = Frame Error occured
[3] Parity Error (PER)
0 = No Frame Error (Receive FIFO-top or HURXBUF)
1 = Frame Error occured
[4] Overrun Error (OER)
0 = No Overrun Error (Receive FIFO-top or HURXBUF)
1 = Overrun Error occured
[5] Control Character Detect (CCD)
0 = No Control Character (Receive FIFO-top or HURXBUF)
1 = Control character present (Receive FIFO-top or HURXBUF)
[6] Data Carrier Detect Lost (DCDL)
0 = DCD pin is Low at the receiver checking time
1 = DCD pin is High at the receiver checking time
[7] Receive FIFO Data Trigger Level Reach (RFREA)
0 = No valid data in HURXBUF or Not reached to trigger level
1 = In RxFIFO mode, RxFIFO has valid data and reach trigger level
In non-FIFO mode, HURXBUF has valid data
[8] Receive FIFO Empty (RFEMT)
0 = Receive FIFO is not empty
[9] Receive FIFO Full (RFFUL)
0 = Receive FIFO is not full
[10] Receive FIFO Overrun (RFOV)
0 = Receive FIFO is not occured
1 = Receive FIFO overrun occured
[11] Receiver in IDLE (IDLE)
0 = Receiver is in IDLE state
1 = Receiver is in active state
Figure 14-3. High-Speed UART Status Register
15 14
13 12 11
10 9
A
T
E
C
D
E
I
R
U
I
_
T
S
_
D
F
B
C
S
R
R
L
O
D
T
X
E
V
D
S
T
N
O
1 = Receive FIFO is empty
1 = Receive FIFO is full
8 7 6
5
4
3
2
R
R
R
D
C
O
P
F
F
F
F
C
C
E
E
E
F
E
R
D
D
R
R
R
U
M
E
L
L
T
A
S3C2500B
1
0
B
R
K
D
D
V
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