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S3C2500B
31
30 29 28 27 26 25
D
D
D
D
P
P
T
T
L
L
x
x
L
L
N
F
T
O
O
D
M
M
[16] Rx abort (RxABT)
0= Normal operation
1 = Seven or more consecutive 1s have been received, in-frame condition.
[17] Rx CRC error (RxCRCE)
0 = Normal operation
1 = A frame Rx operation is completed with a CRC error.
[18] Rx non-octet align (RxNO)
0 = Received frame is octet.
1 = Received frame is not octet.
[19] Rx overrun (RxOV)
0 = Normal operation
1 = Received data is transferred into the RxFIFO when it is full.
[20] Reserved
[21] Reserved
[22] DMA Tx abort (DTxABT)
0 = Normal operation
1 = Abort signal is sended and DMA Tx enable bit is cleared.
[23] Rx internal error (RxIERR)
0 = Normal operation
1 = Received frame is not stable due to receive clock is unstable.
[24] DMA Rx frame done every received frame (DRxFD)
0 = Normal operation
1 = DMA Rx operation has successfully transferred a frame from RxFIFO to buffer memory.
[25] Reserved
[26] DMA Rx not owner (DRxNO)
0 = DMA has the ownership.
1 = CPU has the ownership.
[27] DMA Tx frame done (DTxFD)
0 = Normal operation
1 = DMA Tx operation has successfully transferred a frame from memory to TxFIFO.
[28] Reserved
[29] DMA Tx not owner (DTxNO)
0 = DMA has the ownership.
1 = CPU has the ownership.
[30] DPLL one clock missing (DPLLOM)
0 = Normal operation
1 = Set in FM/Machester mode when DPLL does not detect an edge on the first entry.
[31] DPLL two clock missing (DPLLTM)
0 = Normal operation
1 = DPLL was not detected on two consecutive edges an search mode sas entered.
24
23 22
21
20 19
D
D
R
D
R
R
R
x
T
x
x
x
I
x
O
N
F
E
A
V
O
D
R
B
R
T
Figure 8-15. HDLC Status Register (Continued)
18 17 16
15 14
13 12 11
R
R
R
R
R
R
R
R
x
x
x
x
x
x
x
x
N
C
A
I
F
S
D
F
O
R
B
D
V
D
C
D
C
T
L
C
D
E
E
D
HDLC CONTROLLER
10 9
8 7 6
5
4
3
T
R
T
T
T
T
T
x
x
x
x
x
x
x
F
F
F
F
U
S
C
G
A
C
T
A
C
T
S
S
0
R
x
R
B
8-41
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