Gdma Transfer Count Registers - Samsung S3C2500B User Manual

S3C2500B

12.3.4 GDMA TRANSFER COUNT REGISTERS

The GDMA transfer count register indicates the byte transfer rate, which runs at 24-bit, on GDMA channels 0, 1,
2, 3, 4 and 5.
Whenever GDMA transfer count register transmits the data of GDMA, it will be diminished by transfer width. In
other words, when transfer size (TS) is byte, it will be diminished at 1, in the case of half-word at 2 and word at 4.
If it is set in four data burst mode, each value of GDMA transfer count will be diminished at 4 times. But if the
value of transfer count register is not a multiple of 4 times transfer size, the last misaligned data can be
transferred by one transfer size.
Registers Address
DTCR0 0xF005000C
DTCR1 0xF005002C
DTCR2 0xF005004C
DTCR3 0xF005006C
DTCR4 0xF005008C
DTCR5 0xF00500AC
31
Reserved
Table 12-6. DTCR0/1/2/3/4/5 Registers
R/W
R/W GDMA channel 0 transfer count register
R/W GDMA channel 1 transfer count register
R/W GDMA channel 2 transfer count register
R/W GDMA channel 3 transfer count register
R/W GDMA channel 4 transfer count register
R/W GDMA channel 5 transfer count register
24 23
[23:0] Transfer count
Figure 12-5. GDMA Transfer Count Register
Description
Transfer Count
GDMA CONTROLLER
Reset Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0
12-13