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S3C2500B
31
30
29 28 27 26
O
B S E D
[31:0]
Buffer pointer
[31]
Ownership bit (O) 0 = CPU
[30]
Skip BD (B)
[29]
SOF (S)
[28]
EOF (E)
[27]
Done (D)
[26:16]
Rx status
[26] MSO
[25] Halted
[24] MRx10Stat
[23] BRxDone
[22] RxParErr
[21] MUFS
[20] Overflow
[19] CRCErr
[18] AlignErr
[17] Reserved
[16] Reserved
[15:0]
RxLength
16
Buffer Pointer
Status
Address of the frame data be saved.
Set this bit to skip the current buffer descriptor when the ownership bit is cleared.
Set by the BDMA to indicate the first BD for a frame.
Set by the BDMA to indicate the last BD for a frame.
Set by the BDMA on the first BD when the reception of a frame finished
and it used multiple BD's.
The Rx status field of the received frame.
Rx frame size is larger than the Maximum Rx Frame Size(BRxMFS).
The reception of next frame is halted when MACCON.1 (MHaltImm) is set,
or when MACRXCON.0 (MRxEn) is clear.
The frame was received over 10Mbps(wire-7) interface.
The reception process by the BDMA is done without error.
MRxFIFO Parity Error
Set when the size of the Rx frame is larger than the Maximum Untagged Frame
Size(1518bytes) if the long packet is not enabled in the MAC Rx control register.
MRxFIFO Overflow
CRC at the end of a frame did not match the computed CRC32, or else that
PHY asserted RX_ER during the frame reception.
Set if the frame length in bit is not the multiple of eight and the CRC is invalid.
The byte count of the received data is written in hexa-decimal by the BDMA.
Figure 7-3. Data Structure of Rx Buffer Descriptor
15
RxLength
1 = BDMA
ETHERNET CONTROLLER
0
7-11
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