High-Speed Uart Baud Rate Examples - Samsung S3C2500B User Manual

S3C2500B

14.3.7 HIGH-SPEED UART BAUD RATE EXAMPLES

High-Speed UART BRG input clock, PCLK2 is the system clock frequency divided by 2.
If the system clock frequency is 133 MHz and PCLK2 is selected, the maximum BRGOUT output clock rate is
PCLK2/16 (= 4,156,250 Hz).
EXT_UCLK is the external clock input pin for High-Speed UART, PCLK2, UCLK can be selected by HUCON[6]
register.
PCLK2
EXT_UCLK
Select
Clock
NOTE:
Table 14-14. Typical Baud Rates Examples of High-Speed UART
Baud Rates
(BRGOUT) CNT0
(DEC/HEX)
1200 3463/D87
2400 1731/6C3
4800 865/361
9600 432/160
19200 215/D7
38400 107/6B
57600 71/47
115200 35/23
230400 17/11
460800 8/8
921600 4/4
CNT0
12-bit Counter
CNT0 = CUBRD[15:4], CNT1 = CUBRD[3:0], Select Clock = HUCON[6]
Figure 14-8. High-Speed UART Baud Rate Generator (BRG)
PCLK2 = 66.5 MHz
CNT1 Freq.
0 1199.84
0 2399.68
0 4799.36
0 9598.73
0 19241.90
0 38483.80
0 57725.69
0 115451.39
0 230902.78
0 461805.56
0 831250.00
CNT1
Divide by 1 or 16
EXT_UCLK = 29.4912 MHz
Dev.(%) CNT0
(DEC/HEX)
0.01 1535/5FF
0.01 767/2FF
0.01 383/17F
0.01 191/BF
0.01 95/5F
0.22 47/2F
0.22 31/1F
0.22 15/F
0.22 7/7
0.22 3/3
9.80 1/1
SERIAL I/O (HIGH-SPEED UART)
BRGOUT
Divide by 16
Sample Clock
CNT1 Freq.
0 1200.00
0 2400.00
0 4800.00
0 9600.00
0 19200.00
0 38400.00
0 57600.00
0 115200.00
0 230400.00
0 460800.00
0 921600.00
Dev.(%)
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
14-19