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S3C2500B
31
30
29
X X
X
IOPCON1
Bit
31
30
29
28
27
26
25
24
23
See Note
on 15-1
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7-0
28
27
26
25
23
22
21
24
X
X
X
X
X
X
X
X
Multiplexed signals (0 / 1)
High speed UART nDSR0 (HUARTnDSR0)/GPIO[31]
High speed UART nDTR0 (HUARTnDTR0)/GPIO[30]
High speed UART RTXD0 (HUARTRTXD0)/GPIO[29]
High speed UART RXD0 (HUARTRXD0)/GPIO[28]
Timer Output(TOUT)[5] / GPIO[27]
Timer Output(TOUT)[4] / GPIO[26]
Timer Output(TOUT)[3] / GPIO[25]
Timer Output(TOUT)[2] / GPIO[24]
Timer Output(TOUT)[1] / GPIO[23]
Timer Output(TOUT)[0] / GPIO[22]
xGDMA Ack[3] / GPIO[21]
xGDMA Ack[2] / GPIO[20]
xGDMA Ack[1] / GPIO[19]
xGDMA Ack[0] / GPIO[18]
xGDMA Req[3] / GPIO[17]
xGDMA Req[2] / GPIO[16]
xGDMA Req[1] / GPIO[15]
xGDMA Req[0] / GPIO[14]
External Interrupt(xINT)[5] / GPIO[13]
External Interrupt(xINT)[4] / GPIO[12]
External Interrupt(xINT)[3] / GPIO[11]
External Interrupt(xINT)[2] / GPIO[10]
External Interrupt(xINT)[1] / GPIO[9]
External Interrupt(xINT)[0] / GPIO[8]
Reserved
Figure 15-2. I/O Function Control Register 1 (IOPCON1)
20
19
18
17
16
15
14
13
X
X
X
X
X
X
X
X
12
11
10
9
8
7
Reserved
X
X
X
X
X
IOPCON1
Default signal
default value
HUARTnDSR0
HUARTnDTR0
HUARTTXD0
HUARTRXD0
GPIO[27]
GPIO[26]
GPIO[25]
GPIO[24]
GPIO[23]
GPIO[22]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
GPIO[9]
GPIO[8]
I/O PORTS
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15-5
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