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S3C2500B
31
30 29 28 27 26 25
D
D
D
D
P
P
T
T
L
L
x
x
L
L
N
F
T
O
O
D
M
M
I
I
I
I
E
E
E
E
[3:0] Reserved
[4] Tx frame complete interrupt enable (TxFCIE)
[5] Tx FIFO available to write interrupt enable (TxFAIE)
[6] Reserved
[7] CTS transition has occurred interrupt enable (TxSCTIE)
[8] Transmit underrun has occured interrupt enable (TxUIE)
[9] RxFIFO available to read interrupt enable (RxFAIE)
[10] Tx Frame Good Interrupt enable (TxFGIE)
[11] Flag detected interrupt enable (RxFDIE)
[12] Reserved
[13] DCD transition interrupt enable (RxSDCDIE)
[14] Valid frame interruopt enable (RxFVIE)
[15] Idle detected interruot enable (RxIDLEIE)
[16] Abort detected interrupt enable (RxABTIE)
[17] CRC error frame interrupt enable (RxCRCEIE)
[18] Non-dctet aligned frame interrupt enable (RxNOIE)
[19] Rx overrun interrupt enable (RxOVIE)
[20] Reserved
[21] Reserved
[22] DMA Tx abort interrupt enable (DTxABTIE)
[23] Rx internal error interrupt enable (RxIERRIEN)
[24] DMA Rx frame done every received frame interrupt enable (DRxFDIE)
[25] Reserved
[26] DMA Rx not owner interrupt enable (DRxNOIE)
[27] DMA Tx frame done every received frame interrupt enable (DTxFDIE)
[28] Reserved
[29] DMA Tx not owner interrupt enable (DTxNOIE)
[30] DPLL one missing interrupt enable (DPLLOMIE)
[31] DPLL two missing interrupt enable (DPLLTMIE)
24
21
23 22
20 19
D
D
R
D
R
R
R
x
T
x
x
x
I
x
O
N
F
E
A
V
O
D
R
B
I
I
I
R
T
E
E
E
I
I
E
E
Figure 8-16. HDLC Interrupt Enable Register
18 17 16
15 14
13 12 11
R
R
R
R
R
R
R
x
x
x
x
x
x
x
N
C
A
I
F
S
F
O
R
B
D
V
D
D
I
C
T
L
I
C
I
E
E
I
E
E
D
E
I
E
I
I
E
E
E
HDLC CONTROLLER
10 9
8 7 6
5
4
3
R
T
T
T
T
T
x
x
x
x
x
x
F
F
F
U
S
F
G
A
I
C
A
C
I
I
I
E
T
I
E
E
E
S
E
I
E
0
8-43
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