Samsung S3C2500B User Manual page 104

PROGRAMMER' ' S MODEL
2.16.1.4 Register 2: Instruction and data cacheable registers
This location provides access to two registers which contain the cacheable attributes for each of eight memory
areas. The two registers provide individual control for the I and D address spaces. The opcode_2 field determines
whether the instruction-or data-cacheable attributes are programmed:
If the opcode_2 field = 0, the data-cacheable bits are programmed. For example:
MCR p15,0,Rd,c2,c0,0; Write data-cacheable bits
MRC p15,0,Rd,c2,c0,0; Read data-cacheable bits
If the opcode_2 field = 1 the instruction-cacheable bits are programmed. For example:
MCR p15,0,Rd,c2,c0,1; Write instruction cacheable bits
MRC p15,0,Rd,c2,c0,1; Read instruction cacheable bits
The format for the data and instruction cacheable bits is similar, as shown in Table 2-10. Setting a bit makes an
area cacheable, clearing it makes it non-cacheable.
All defined bits in the control register are set to zero at reset.
Register Bits
7
6
5
4
3
2
1
0
2-24
Table 2-10. Cacheable Register Format
Cacheable bit (C_7) for area 7
Cacheable bit (C_6) for area 6
Cacheable bit (C_5) for area 5
Cacheable bit (C_4) for area 4
Cacheable bit (C_3) for area 3
Cacheable bit (C_2) for area 2
Cacheable bit (C_1) for area 1
Cacheable bit (C_0) for area 0
Functions
S3C2500B