Hdlc External Pin Multiplexed Signals; Operation - Samsung S3C2500B User Manual

IOM2 CONTROLLER

9.4.3 HDLC EXTERNAL PIN MULTIPLEXED SIGNALS

HDLC external pins are multiplexed among the various operating modes. The Mode bits in TSAxCON determines
operating mode of each TSA and HDLC external pins are automatically configured according to Mode bits as
follows.
Channel
A DCE_TXCA
DCE_TXDA
DCE_RXCA
DCE_RXDA
B DCE_TXCB
DCE_TXDB
DCE_RXCB
DCE_RXDB
C DCE_TXCC
DCE_TXDC
DCE_RXCC
DCE_RXDC

9.4.4 OPERATION

The Time Slot Assigner (TSA) controllers are configured as follows:
1. Configure the TSAxCON register.
— Define the start bit position for each TSA.
— Define the stop bit position for each TSA.
— Determine operating mode for each TSA (DCE, PCM highway (non-multiplexed or multiplexed),
and IOM2 interface)
2. Enable TSA by setting TSAEN bit in IOM2CON[13] to "1".
3. Program each intended HDLC channel
9.4.4.1 Clock Divide
In PCM mode, the TSA provides each HDLC channel with proper clock according to its programmed timeslot. In
this process, the clock frequency is either the same as or 1/2 times that of the external clock. When the Divide bit
in TSAxCON is set to "1", each HDLC channel is provided with half frequency clock of external clock and the tx
data is shifted out every two external clock. When the Divide bit in TSAxCON is "0", each HDLC channel is
provided with the external clock and the tx data is shifted out every one clock.
9-10
Table 9-1. HDLC External Pin Multiplexed Signals
External Interface
DCE
Multiplexed
PCM_FSCB
PCM_TXDB
PCM_DCLB
PCM_RXDB
PCM
Non-multiplexed
PCM_FSCA
PCM_TXDA
PCM_DCLA
PCM_RXDA
PCM_FSCB
PCM_TXDB
PCM_DCLB
PCM_RXDB
PCM_FSCC
PCM_TXDC
PCM_DCLC
PCM_RXDC
Default Signal
IOM2
IOM2_FSC DCE_TXCA
IOM2_DU DCE_TXDA
IOM2_DCL DCE_RXCA
IOM2_DD DCE_RXDA
– DCE_TXCB
– DCE_TXDB
– DCE_RXCB
– DCE_RXDB
– DCE_TXCC
– DCE_TXDC
– DCE_RXCC
– DCE_RXDC
S3C2500B