Samsung S3C2500B User Manual page 315

S3C2500B
7.3.4.5 Threshold Logic and Counters
The transmission state machine uses a counter and logic to control the threshold of when the transmission can
begin. Before transmitting the MAC waits until eight bytes or a complete frame has been placed in the
MTxFIFO. This gives the DMA engine some latency without causing an underflow during transmission.
7.3.4.6 Back-Off and Retransmit Timers
When a collision is detected on the network, the transmitter block stops the transmission and starts a jamming
pattern to ensure that all the nodes detect the collision. After this, the transmitter waits for a minimum of 96 bit
times and then retransmits the data. After 16 attempts, the transmission state machine sets an error bit and
generates an interrupt, if enabled, to signify the failure to transmit a frame due to excessive collisions. It flushes
the MTxFIFO, and the MAC is ready for the next frame.
7.3.4.7 Transmit Data Parity Checker
Data in the FIFO is even-parity. When data is read for transmission, the transmission state machine checks the
parity. If a parity error is detected, the transmit data parity checker does the following:
•
It stops transmission.
• •
It sets the parity error bit in the transmit status register.
•
It generates an interrupt, if enabled.
7.3.4.8 Transmission State Machine
The transmission state machine is the central control logic for the transmitter block. It controls the passing of
signals, the timers, and the posting of errors in the status registers.
ETHERNET CONTROLLER
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