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S3C2500B
6
2
I
C CONTROLLER
6.1 OVERVIEW
The S3C2500B has internal I
serial clock lines (SCL). When the I
number of IC is limited only by the maximum bus capacitance of 400 pF.
6.2 FEATURES
•
Supports only single master mode.
•
Supports 8-bit, bi-directional, serial data transfers.
•
Supports 7-bit addressing.
Figure 6-1 shows a block diagram of the S3C2500B I
Data
SDA
Control
Serial Clock
SCL
Line Control
2
C (or IIC) controller. It requires only two bus lines, a serial data line (SDA) and a
2
C is free, both lines are high level. It is connected to the same I
Serial
Clock
Prescaler
16
RESET
BUSY
COND1 COND0
Figure 6-1. I
2
C controller
Shift buffer register (IICBUF)
System clock (f
)
SYSCLK
Prescaler register (IICPS)
ACK
Control status register (IICCON)
2
C Block Diagram
2
I
C CONTROLLER
2
C. And the
LRB
IEN
BF
6-1
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