Block And Four Data Burst - Samsung S3C2500B User Manual

S3C2500B
12.6.4 BLOCK AND FOUR DATA BURST (DCON[3:1] = 001, [4] = 1, [5] = 1)
This timing diagram is the same with block and one data burst, except that it is four data burst.
HCLK
xGDMA_Req
xGDMA_Ack
Address
Data
a
NOTE: ' ' is in the block mode, GDMA starts to operate with first xGDMA_Req signal. So in the ideal case,
GDMA does not care the number of xGDMA_Req signal pulse. But I recommand that xGDMA_Req
siganl is deasserted when xGDMA_Ack signal is active state.
one data burst; source address0 and source data0 → destination address0 and destination data0 → ....
four data burst; source address0 and source data0 → source address1 and source data1 → source address2
and source data2 → source address3 and source data3 → destination address0 and destination
data0 → destination address1 and destination data1 → destination address2 and destination
data2 → destination address3 and destination data3 → source address4 and source data4 → ...
In four data burst mode, GDMA transfers four data and GDMA Transfer Count Register (DTCR) value
decreases by four.
Recommand
deasserted time
Programmable by
DCON[16:13]
SA0 SA1
SD0
Figure 12-14. Block and Four Data Burst Timing
a
SA2 SA3 DA0
SD1 SD2 SD3
NOTE
GDMA CONTROLLER
DA1 DA2 DA3
DD0 DD1 DD2 DD3
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