Samsung S3C2500B User Manual page 111

S3C2500B
2.16.1.8.4 Drain Write Buffer
This CP15 operation causes instruction execution to be stalled until the write buffer is emptied. This operation is
useful in real time applications where the processor needs to be sure that a write to a peripheral has completed
before program execution continues. An example would be where a peripheral in a bufferable region is the
source of an interrupt. Once the interrupt has been serviced, the request must be removed before interrupts can
be re-enabled. This can be ensured if a drain write buffer operation separates the store to the peripheral and the
enable interrupt functions.
The drain write buffer function is invoked by a write to CP15 register 7 using the following ARM instruction:
MCR p15, 0, Rd, c7, c10, 4
This stalls the processor core, with CPnWAIT asserted until any outstanding accesses in the write buffer have
been completed (that is, until all data has been written to memory).
2.16.1.9 Register 9: Instruction and data lockdown registers
These registers allow regions of the cache to be locked down. The opcode_2 field determines whether the
instruction or data caches are programmed.
•
If the opcode_2 field = 0, the data lockdown bits are programmed. For example:
MCR/MRC p15, 0, Rd, c9, c0, 0; data lockdown control
•
If the opcode_2 field = 1, the instruction lockdown bits are programmed. For example:
MCR/MRC p15, 0, Rd, c9, c0, 1; instruction lockdown control
The format of the registers, Rd, transferred during this operation, is shown below:
All defined bits in the control register are set to zero at reset.
NOTE: The segment number is not specified because cache lines are locked down across all four segments
(16-word granularity).
Table 2-21. Lockdown Register Format
Register bit
31
30:6
5:0
Function
Load bit
Reserved
Cache index
PROGRAMMER' ' S MODEL
2-31