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SERIAL I/O (HIGH-SPEED UART)
Table 14-4. High-Speed UART Control Register Description (Continued)
Bit Number
Receive FIFO trigger
level (RFTL)
[23:22]
[24]
Data Terminal Ready to
pin (DTR)
[25]
Request to Send to pin
(RTS)
[27:26]
Reserved
[28]
Hardware Flow Control
Enable (HFEN)
[29]
Software Flow Control
Enable (SFEN)
[30]
Echo Mode
(ECHO)
[31]
RTS/RTR selection
(RTS/RTR)
14-6
Bit Name
This two bit trigger level value determines when the receiver start to
move the received data in 32-byte receive FIFO.
00 = 1-byte valid/32-byte
10 = 18/32
This bit directly controls the HUnDTR0/HUnDTR1 pin. Setting this
bit to one, the HUnDTR0/HUnDTR1 pin goes to Low level. If you set
this bit to zero, it goes High level.
This bit directly controls the High-Speed UARTS pin only when the
High-Speed UART is not hardware flow control mode. If this bit set
to one, High-Speed UARTS pin goes Low level. Otherwise, it
remains High level.
This bit should be cleared by zero.
This bit determines whether High-Speed UART select hardware flow
control or not. If this bit set to one, High-Speed UART will control all
pins concerning to hardware flow control.
This bit determines whether High-Speed UART select software flow
control or not. If this bit set to one, High-Speed UART will act in
software flow control.
In this mode, you have to use Control Character register.
If this bit is set to one, RX data is sent not only HURXBUF but also
TX port directly, so HUTXBUF data will not be transmitted.
This selection bit determines output of HUnRTS0/HUnRTS1 pin
0 = RTS
1 = RTR
NOTE: In RxFIFO mode, RTR goes to '1' when RxFIFO is full,
Description
In nonRxFIFO mode, RTR goes to '1' when RxBUF is not empty.
01 = 8/32
11 = 28/32
S3C2500B
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