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HDLC CONTROLLER
8.7.3 HDLC STATUS REGISTER (HSTAT)
Reading the HDLC status register is a non-destructive process. The method used to clear a High-level
status condition depends on the bit's function and operation mode(DMA or interrupt). For details, please
see the description of each status register.
Registers
HSTATA
0×F0100008
HSTATB
0×F0110008
HSTATC
0×F0120008
8.7.4 SUMMARY
There are two kinds of bits in a status register.
1. TxFA, TxCTS, RxFA, RxDCD, RxFV, RxCRCE, RxNO, RxIERR, and RxOV bits are show each bit's
status. These bits are set or cleared automatically according to the each bit status.
2. All other bits are cleared by the CPU writing '1' to each bit.
8-36
Table 8-11. HSTATA, HSTATB, and HSTATC Register
Address
R/W
R/W
R/W
R/W
NOTE
Description
HDLC Channel A Status Register
HDLC Channel B Status Register
HDLC Channel C Status Register
S3C2500B
Reset Value
0X00000000
0X00000000
0X00000000
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